The present invention relates generally to signal processing circuitry and in particular the present invention relates to clock signals and data signals separator circuits.
In an integrated circuit environment, it is possible to have two subsystems on one chip that communicate with each other or one subsystem on one chip and a second subsystem on another chip which communicates with each other. This environment may include communication errors when a local clock of a local system samples incoming data signals from a remote subsystem. That is, synchronization between clock and data signals may not always be maintained. For communications to remain error-free, the local system needs to maintain synchronization with the remote system. In other words, it is imperative that the sender and receiver sample the data signal in sync.
Near-perfect synchronization could be accomplished if both the sender and the receiver used the same clock. However, this isn""t practical because of the many different systems and many interfaces that are necessary. Hence, for practical reasons the local receiver is periodically synchronized with the remote transmitter. The clocks of each system maintain sampling integrity between synchronization pulses. A common technique is to synchronize source signals, e.g., a clock signal and a data signal.
Less than perfect synchronization that results in data errors, is in general referred to as data meta-stability. This is because various data signals can arrive at any time and their edges/transitions that represent the occurrence of some event can also arrive at unpredictable moments in time. This phenomenon typically occurs when converting from asynchronous to synchronous communication. The terms xe2x80x9casynchronousxe2x80x9d and xe2x80x9csynchronousxe2x80x9d are well known in the art. However, some designers also refer to the process of retrieving data after sampling an unknown edge, with respect to the local system receiving the data under the local clock, as asynchronous.
Special circuitry, otherwise known as a signal separator circuit, determine when data signal edges and clock pulse edges occur nearly simultaneously and when they do not. In other words, the signal separator circuit performs a signal processing operation when the two signals coincide. The separation of the signals (clock and data) is desired when a device such as a flip-flop has to re-sample the data and correctly interpret it. A flip-flop, or similar circuitry, has to have enough time to resolve the correct value of the data. In the past, inductors/transformers were used as part of the data meta-stability solvers.
The electronic industry has grown tremendously because of the ability of chip designers and chip manufacturers to constantly shrink the chip while increasing the number of components on the chip, while decreasing cost. Because integrated circuit real estate is expensive, bulky inductors are not desired. For example, a designer utilizing inductor technology may need to reserve approximately a 200xc3x97200 micron area of chip real estate specifically for the inductor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for economical circuitry that separates data signal edges and clock pulse edges.
The above mentioned problems and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a signal processing circuit comprises a data input node to receive a data input signal, and a clock input signal node to receive a clock input signal. In addition, a signal separator circuit is coupled to the data input node and the clock input node such that transitions in the data input signal and transitions in the clock input signal have a first time differential. The signal separator circuit itself comprises a data output node and a clock output node. Within the signal separator circuit pass gate transistors can be selectively activated to provide an output data signal on the data output node and an output clock signal on the clock output node wherein transitions in the output data signal and transitions in the output clock signal have a second time differential that is greater than the first time differential. Subsequently, a latch circuit is coupled to the signal separator circuit for receiving the output clock signal and the output data signal.
In another embodiment, a signal processing circuit comprises receiving a data input signal at a data input node, and receiving a clock input signal at a clock input signal node. A signal separator circuit is coupled to the data input node and the clock input node. The signal separator circuit comprises a first P-channel transistor coupled in series with a first N-channel transistor, wherein the gate connections of the first P-channel transistor and the first N-channel transistor are coupled to the data input node. The signal separator circuit also comprises a second P-channel transistor coupled in series with a second N-channel transistor, wherein the gate connections of the second P-channel transistor and the second N-channel transistor are coupled to the clock input node. A third P-channel transistor is coupled to the first and second P-channel transistors. Moreover, the circuit includes a flip-flop circuit and two inverter circuits. The first inverter circuit is coupled between a data output node of the signal separator circuit and the flip-flop circuit. The second inverter circuit is coupled between a clock output node of the signal separator circuit and the flip-flop circuit.
In yet another embodiment, in a method a clock input signal that undergoes a clock transition and a data input signal that undergoes a data transition are received at a signal separator. Upon analyzing the synchronization of the data transition with the clock transition, a person skilled in the art can increase the delay between the clock transition and the data transition, by implementing CMOS circuitry to form pass gate circuitry, provided that the clock transition is substantially synchronized with the data transition.